1. Field of the Invention
The invention relates to a vertical metal oxide semiconductor field effect transistor (MOSFET) and a manufacturing method thereof and more particularly, to a vertical MOSFET which has a gate electrode made of polycrystalline silicon doped with p-type and n-type impurities and a manufacturing method thereof.
2. Description of the Related Art
Generally, a vertical MOSFET has a source electrode and a gate electrode made of polycrystalline silicon which are laminated on the surface of an epitaxial layer formed on a silicon substrate. The MOSFET has a drain electrode on the reverse surface of the substrate. A source region is formed in the surface area of the epitaxial layer and a channel is formed in a surface region, which is in contact with the gate oxide film, of the epitaxial layer. The substrate and epitaxial layer serve as a drain region.
For a conventional vertical MOSFET, phosphorus (P) is ion-implanted into a polycrystalline silicon film forming a gate electrode to make the conductivity type of the MOSFET n, so that the sheet resistance of the film becomes about 10 .OMEGA./.quadrature. to lessen the gate resistance, namely, gate electrode resistance. If the gate resistance is small, a high switching speed is provided as understood From the following expression: EQU t=f(1/CR.sub.G) (1)
where t is the switching speed, C is the gate capacitance, and R.sub.G is the gate resistance.
On the other hand, the threshold voltage of an FET, V.sub.T, is generally represented by the following expression: EQU V.sub.T =.phi..sub.MS -(Q.sub.SS /C.sub.0)+2.phi..sub.f -(Q.sub.B /C.sub.0)(2)
where .phi..sub.MS is the work function difference between the gate electrode material and the substrate semiconductor, Q.sub.SS is the charge on the surfaces of the gate oxide film side of the substrate semiconductor, Q.sub.B is the charge of the depletion layer of the substrate semiconductor, C.sub.O is the gate oxide film capacitance, and .phi..sub.f is the Fermi level of the substrate semiconductor.
The work function difference .phi..sub.MS is substantially 0 V between the n-type polycrystalline silicon of the gate electrode and the n-type single crystal silicon of the substrate. As understood from the expression (2), when the gate electrode is made of n-type polycrystalline silicon, the absolute value of the threshold voltage V.sub.T is greater by about 0.9 V than the case where it is made of p-type polycrystalline silicon. Thus, it is difficult to drive the FET at low voltage although the switching speed of the FET becomes high.
If boron (B) rather than phosphorus is ion-implanted into a polycrystalline silicon film as a gate electrode to make conductivity type p, some boron ions pass through the gate oxide film even if thermal processing for the p-type polycrystalline silicon film is performed at a temperature of about 900.degree. C. as a result, the FETs vary in threshold voltage V.sub.T.